Modern computer systems typically require some method of memory management to provide for dynamic memory allocation. In the case of a system with one or more co-processors, some method is necessary to synchronize between the dynamic allocation of memory and the use of that memory by a co-processor.
In a typical hardware configuration of a CPU with a specialised co-processor, both share a bank of memory. In such a system, the CPU is the only entity in the system capable of allocating memory dynamically. Once allocated by the CPU for use by the co-processor, this memory can be used freely by the co-processor until it is no longer required, at which point it is able to be freed by the CPU. This implies that some form of synchronization is necessary between the CPU and the co-processor in order to ensure that the memory is released only after the co-processor is finished using it.
Several possible solutions to this problem have undesirable performance implications. Use of statically allocated memory would avoid the need for synchronization, but would prevent the system from adjusting its memory resource usage dynamically. Alternatively, having the CPU block and wait until the co-processor has finished performing each operation would substantially reduce parallelism and hence reduce the overall system performance. Similarly, the use of interrupts to indicate completion of operations by the co-processor would also impose significant processing overhead if co-processor throughput is very high. So these prior art solutions are not attractive.
In addition to the need for high performance, such a system also has to deal with dynamic memory shortages gracefully. Most computer systems allow a wide range of memory size configurations. It is important that a system with large amounts of memory available to it make full use of the available resources to maximise performance. However, systems with minimal configurations must still perform adequately to be usable and at the very least degrade gracefully in the face of a memory shortage.
To overcome these problems, a synchronization mechanism is desired which will maximise system performance while also allowing co-processor memory usage to adjust dynamically to both the capacity of the system, and the complexity of the operation being performed. The present invention is based upon the realisation that after co-processor instructions have been completed, they can be placed in a "clean-up" queue and from time to time the memory resources allocated to these executed instructions can be reallocated by the CPU.